View MSM51V4221C-40RD_2585006.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

feds51v4221c-03 1 semiconductor this version: oct. 2000 previous version: feb. 2000 msm51v4221c 262,263-word 4-bit field memory 1/16 general description the oki msm51v4221c is a high performance 1-mbit, 256k 4-bit, field memory. it is designed for high- speed serial access applications such as hdtvs, conventional ntsc tvs, vtrs, digital movies and multi-media systems. it is a fram for wide or low end use as general commodity tvs and vtrs, exclusively. the msm51v4221c is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture, and data storage systems and others. the 1-mbit capacity fits one field of a conventional ntsc tv screen. each of the 4-bit planes has separate serial write and read ports. these employ independent control clocks to support asynchronous read and write operations. different clock rates are also supported that allow alternate data rates between write and read data streams. the msm51v4221c provides high speed fifo, first-in first-out, operation without external refreshing: it refreshes its dram storage cells automatically, so that it appears fully static to the users. moreover, fully static type memory cells and decoders for serial access enable refresh free serial access operation, so that the serial read and/or write control clock can be halted high or low for any duration as long as the power is on. internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. the msm51v4221b?s function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. the delay length, number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. additional sram serial registers, or line buffers for the initial access of 256 4-bit enable high speed first-bit- access with no clock delay just after the write or read reset timings. the msm51v4221c is similar in operation and functionality to oki 2-mbit field memory msm51v8221a.
feds51v4221c-03 1 semiconductor msm51v4221c 2/16 features ? single power supply: 3.3 v 0.3 v ? 512 rows 512 column 4 bits ? fast fifo (first-in first-out) operation ? high speed asynchronous serial access read/write cycle time 30 ns/40 ns access time 30 ns/35 ns ? functional compatibility with oki msm51v8221a ? self refresh (no refresh control is required) ? package options: 16-pin 300 mil plastic dip (dip16-p-300-2.54) (product: msm51v4221c-xxra) 26/20-pin 300 mil plastic soj (soj26/20-p-300-1.27) (product: msm51v4221c-xxja) 20-pin 400 mil plastic zip (zip20-p-400-1.27) (product: msm51v4221c-xxrd) xx indicates speed rank. product family family access time (max.) cycle time (min.) package msm51v4221c-30ra 30 ns 30 ns msm51v4221c-40ra 35 ns 40 ns 300 mil 16-pin dip msm51v4221c-30ja 30 ns 30 ns msm51v4221c-40ja 35 ns 40 ns 300 mil 26/20-pin soj msm51v4221c-30rd 30 ns 30 ns MSM51V4221C-40RD 35 ns 40 ns 400 mil 20-pin zip
feds51v4221c-03 1 semiconductor msm51v4221c 3/16 pin configuration (top view) pin name function swck serial write clock srck serial read clock we write enable re read enable rstw write reset clock rstr read reset clock d in 0 to 3 data input d out 0 to 3 data output v cc power supply (3.3 v) v ss ground (0 v) nc no connection 20-pin plastic zip no lead 3 4 5 9 10 11 12 13 swck nc nc 24 23 22 18 17 16 15 14 rstr srck nc nc 2 rstw 25 re 1 we 26 26/20-pin plastic soj 19 1 3 5 7 9 11 13 15 17 srck re we swck nc nc 2 4 6 8 12 14 16 18 20 rstr rstw nc 16-pin plastic dip 1 we 2 rstw 3 swck 4 d in 0 5 6 7 8 v ss 16 15 re 14 rstr 13 srck 12 d out 0 11 10 9 d in 1 d in 2 d in 3 v cc d out 1 d out 2 d out 3 d in 0 d in 1 d in 2 d in 3 v ss v cc d out 0 d out 1 d out 2 d out 3 v cc d in 0 d in 2 v ss d out 0 d out 2 d in 1 d in 3 d out 1 d out 3
feds51v4221c-03 1 semiconductor msm51v4221c 4/16 block diagram read line buffer low-half ( 4) read line buffer high-half ( 4) 512-word serial read register ( 4) serial read controller re rstr srck data-out buffer ( 4) 120-word sub-register ( 4) d out ( 4) 120-word sub-register ( 4) 256 ( 4) 256 ( 4) 256k ( 4) memory array x decoder read/write and refresh controller 256 ( 4) 256 ( 4) write line buffer low-half ( 4) write line buffer high-half ( 4) 512-word serial write register ( 4) clock oscillator serial write controller we rstw swck data-in buffer ( 4) d in ( 4) v bb generator
feds51v4221c-03 1 semiconductor msm51v4221c 5/16 operation write operation the write operation is controlled by three clocks, swck, rstw, and we. write operation is accomplished by cycling swck, and holding we high after the write address pointer reset operation or rstw. each write operation, which begins after rstw, must contain at least 130 active write cycles, i.e. swck cycles while we is high. to transfer the last data to the dram array, which at that time is stored in the serial data registers attached to the dram array, an rstw operation is required after the last swck cycle. write reset: rstw the first positive transition of swck after rstw becomes high resets the write address counters to zero. rstw setup and hold times are referenced to the rising edge of swck. because the write reset function is solely controlled by the swck rising edge after the high level of rstw, the states of we are ignored in the write reset cycle. before rstw may be brought high again for a further reset operation, it must be low for at least two swck cycles. data inputs: d in 0 to 3 write clock: swck the swck latches the input data on chip when we is high, and also increments the internal write address pointer. data-in setup time t ds , and hold time t dh are referenced to the rising edge of swck. write enable: we we is used for data write enable/disable control. we high level enables the input, and we low level disables the input and holds the internal write address pointer. there are no we disable time (low) and we enable time (high) restrictions, because the msm51v4221c is in fully static operation as long as the power is on. note that we setup and hold times are referenced to the rising edge of swck.
feds51v4221c-03 1 semiconductor msm51v4221c 6/16 read operation the read operation is controlled by three clocks, srck, rstr, and re. read operation is accomplished by cycling srck, and holding re high after the read address pointer reset operation or rstr. each read operation, which begins after rstr, must contain at least 130 active read cycles, i.e. srck cycles while re is high. read reset: rstr the first positive transition of srck after rstr becomes high resets the read address counters to zero. rstr setup and hold times are referenced to the rising edge of srck. because the read reset function is solely controlled by the srck rising edge after the high level of rstr, the states of re are ignored in the read reset cycle. before rstr may be brought high again for a further reset operation, it must be low for at least two srck cycles. data out: d out 0 to 3 read clock: srck data is shifted out of the data registers. it is triggered by the rising edge of srck when re is high during a read operation. the srck input increments the internal read address pointer when re is high. the three-state output buffer provides direct ttl compatibility (no pullup resistor required). data out is the same polarity as data in. the output becomes valid after the access time interval t ac that begins with the rising edge of srck. there are no output valid time restriction on msm51v4221c. read enable: re the function of re is to gate of the srck clock for incrementing the read pointer. when re is high before the rising edge of srck, the read pointer is incremented. when re is low, the read pointer is not incremented. re setup times (t rens and t rdss ) and re hold times (t renh and t rdsh ) are referenced to the rising edge of the srck clock.
feds51v4221c-03 1 semiconductor msm51v4221c 7/16 power-up and initialization on power-up, the device is designed to begin proper operation after at least 100 s after v cc has stabilized to a value within the range of recommended operating conditions. after this 100 s stabilization interval, the following initialization sequence must be performed. because the read and write address counters are not valid after power-up, a minimum of 130 dummy write operations (swck cycles) and read operations (srck cycles) must be performed, followed by an rstw operation and an rstr operation, to properly initialize the write and the read address pointer. dummy write cycles/rstw and dummy read cycles/rstr may occur simultaneously. if these dummy read and write operations start while v cc and/or the substrate voltage has not stabilized, it is necessary to perform an rstr operation plus a minimum of 130 srck cycles plus another rstr operation, and an rstw operation plus a minimum of 130 srck cycles plus another rstw operation to properly initialize read and write address pointers. old/new data access there must be a minimum delay of 600 swck cycles between writing into memory and reading out from memory. if reading from the first field starts with an rstr operation, before the start of writing the second field (before the next rstw operation), then the data just written will be read out. the start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 119 swck cycles. if the rstr operation for the first field read-out occurs less than 119 swck cycles after the rstw operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. the first field of data that is read out while the second field of data is written is called ?old data?. in order to read out ?new data?, i.e., the second field written in, the delay between an rstw operation and an rstr operation must be at least 600 srck cycles. if the delay between rstw and rstr operations is more than 120 but less than 600 cycles, then the data read out will be undetermined. it may be ?old data? or ?new? data, or a combination of old and new data. such a timing should be avoided.
feds51v4221c-03 1 semiconductor msm51v4221c 8/16 electrical characteristics absolute maximum ratings parameter symbol condition rating unit input output voltage v t at ta = 25 c, v ss ?1.0 to 4.6 v output current i os ta = 25 c50ma power dissipation p d ta = 25 c1w operating temperature t opr ? 0 to 70 c storage temperature t stg ? ?55 to 150 c recommended operating conditions parameter symbol min. typ. max. unit power supply voltage v cc 3.0 3.3 3.6 v power supply voltage v ss 000v input high voltage v ih 2.4 v cc v cc + 0.3 v input low voltage v il ?0.3 0 0.8 v dc characteristics parameter symbol condition min. max. unit input leakage current i li 0 < v i < v cc , other pins tested at v = 0 v ?10 10 a output leakage current i lo 0 < v o < v cc ?10 10 a output ?h? level voltage v oh i oh = ?1 ma 2.4 ? v output ?l? level voltage v ol i ol = 2 ma ? 0.4 v operating current i cc1 minimum cycle time, output open ? 30 ma standby current i cc2 input pin = v ih /v il ?3ma capacitance (ta = 25c, f = 1 mhz) parameter symbol max. unit input capacitance (d in , swck, srck, rstw, rstr, we, re) c i 7pf output capacitance (d out )c o 7pf
feds51v4221c-03 1 semiconductor msm51v4221c 9/16 ac characteristics (v cc = 3.3 v 0.3 v, ta = 0 to 70c) msm51v4221c-30 msm51v4221c-40 parameter symbol min. max. min. max. unit access time from srck t ac ?30?35ns d out hold time from srck t ddck 6?6?ns d out enable time from srck t deck 630635ns d out hold time from re t ddre 9?9?ns swck ?h? pulse width t wswh 12 ? 17 ? ns swck ?l? pulse width t wswl 12 ? 17 ? ns input data setup time t ds 3?5?ns input data hold time t dh 6?6?ns we enable setup time t wens 0?0?ns we enable hold time t wenh 5?5?ns we disable setup time t wdss 0?0?ns we disable hold time t wdsh 5?5?ns we ?h? pulse width t wweh 5?10?ns we ?l? pulse width t wwel 5?10?ns rstw setup time t rstws 0?0?ns rstw hold time t rstwh 10 ? 10 ? ns srck ?h? pulse width t wsrh 12 ? 17 ? ns srck ?l? pulse width t wsrl 12 ? 17 ? ns re enable setup time t rens 0?0?ns re enable hold time t renh 5?5?ns re disable setup time t rdss 0?0?ns re disable hold time t rdsh 5?5?ns re ?h? pulse width t wreh 5?10?ns re ?l? pulse width t wrel 5?10?ns rstr setup time t rstrs 0?0?ns rstr hold time t rstrh 10 ? 10 ? ns swck cycle time t swc 30 ? 40 ? ns srck cycle time t src 30 ? 40 ? ns transition time (rise and fall) t t 330330ns
feds51v4221c-03 1 semiconductor msm51v4221c 10/16 notes: 1. input signal reference levels for the parameter measurement are v ih = 3.0 v and v il = 0 v. the transition time t t is defined to be a transition time that signal transfers between v ih = 3.0 v and v il = 0 v. 2. ac measurements assume t t = 3 ns. 3. read address must have more than a 600 address delay than write address in every cycle when asynchronous read/write is performed. 4. read must have more than a 600 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called ?new data read?. when read has less than a 119 address delay than write, the read data are the data written in a previous series of write cycles which had been written before at last write reset cycle: this is called ?old data read?. 5. when the read address delay is between more than 120 and less than 599, read data will be undetermined. however, normal write is achieved in this address condition. 6. outputs are measured with a load equivalent to 1 ttl load and 30 pf. output reference levels are v oh = 2.0 v and v ol = 0.8 v.
feds51v4221c-03 1 semiconductor msm51v4221c 11/16 timing waveform write cycle timing (write reset) write cycle timing (write enable) swck we rstw n n + 2 n cycle disable cycle disable cycle n + 1 cycle t wenh t wdss t wens t wwel t wweh t wdsh n + 1 ?v ih ?v il ?v ih ?v il ?v ih ?v il ?v ih ?v il d in swck rstw d in we n0 12 3 n cycle 0 cycle 1 cycle 2 cycle t t t rstws t rstwh t swc t ds t dh t wswh t wswl ?v ih ?v il ?v ih ?v il ?v ih ?v il ?v ih ?v il
feds51v4221c-03 1 semiconductor msm51v4221c 12/16 read cycle timing (read reset) read cycle timing (read enable) srck re d out rstr n ? 1 n + 1 ?v ih n cycle disable cycle disable cycle n + 1 cycle t renh t wrel t rdsh t rdss t wreh n hi-z t ddre t deck t rens ?v il ?v ih ?v il ?v ih ?v il ?v oh ?v ol srck rstr d out re n ? 1 n 012 n cycle 1 cycle 2 cycle t src t t t rstrs t rstrh t wsrl t wsrh t ac t ddck 0 cycle ?v ih ?v il ?v ih ?v il ?v ih ?v il ?v oh ?v ol
feds51v4221c-03 1 semiconductor msm51v4221c 13/16 package dimensions dip16-p-300-2.54 package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.99 typ. 5 rev. no./last revised 2/dec. 11, 1996 ( unit: mm )
feds51v4221c-03 1 semiconductor msm51v4221c 14/16 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj26/20-p-300-1.27 mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.80 typ. 5 rev. no./last revised 5/dec. 5, 1996 (unit: mm)
feds51v4221c-03 1 semiconductor msm51v4221c 15/16 zip20-p-400-1.27 mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.50 typ. 5 rev. no./last revised 3/dec. 5, 1996 (unit: mm)
feds51v4221c-03 1 semiconductor msm51v4221c 16/16 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2000 oki electric industry co., ltd .

▲Up To Search▲

Price & Availability of MSM51V4221C-40RD

	To Download MSM51V4221C-40RD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .